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The FB100A is a modular, expandable, high data
rate BER (Bit Error Rate) test system. With operation
from DC to 160 Mb/s, serial and/or parallel data
interfacing and INSTALOK™ synchronization,
the versatility of the FB100A provides the flexibility
to connect to most users' terminal equipment or
evaluation boards and simply setup and run a test.
Fast Bit's FB100A is designed to plug in and
connect to almost any commercial modulator, demodulator
(i.e. modem) or set top box evaluation board.
The data generator and error detector offer parallel
interfacing through specially designed “PODs”,
with a choice of logic levels. The clock and data
signals can also be complemented with two supplemental
I/O signals, programmed to your specific handshaking
requirements (e.g. DVALID, PSYNC) to meet the
requirements of asynchronous receivers.
Generator
The generator's internal pseudo-random pattern
generator and 4Mb pattern memories can be used
together to output standard pseudo-random patterns
with payload / overhead frame type structures.
Once constructed, patterns can be serial to parallel
shifted to create unique parallel 8-bit WORD outputs
through the pods, or transmitted as a serial data
stream.
New G.703 Interface POD
The new G.703 Interface Pod option now allows the Aeroflex FB100A bit error rate tester to test a wide range of standardized telecommunications interfaces (from T1 at 1.544 Mbit/s to STS-3 and STM-1 at 155.52 Mbit/s). This improvement greatly increases the variety of equipment on which bit error rate measurements and noise/error characterization can be made.
The G.703 Interface Pod enables the FB100A to provide a fully integrated test system for R&D and manufacturing that wasn’t previously possible with the FB100A. Adding the optional G.703 pod and optional noise generation capabilities to the FB100A with its automatic and highly accurate carrier-to-noise-level calibration, gives users a comprehensive test solution ideal for effectively characterizing error/noise performance.
Analyzer
The analyzer receives data from the device under
test (D.U.T.), from the serial or the parallel
inputs, for comparison to its own internally generated
patterns. Fast Bit's INSTALOK™ technology
deciphers framing and payload synchronization
immediately to the incoming data stream. Complex
patterns, such as used in Framed Data protocols,
are synchronized using the “mixed pseudo-random
and memory pattern” mode, providing quick
Frame/Word Header synchronization for the ‘overhead’
and a separate ‘feed-forward’ synchronization
for the pseudo-random ‘payload’. This
allows rapid and independent payload / overhead
synchronization. The Analyzer also provides the
user with separate, programmable 4 Mb memory,
so the analyzed data streams can be completely
different from the that which is generated.
Test Results
The analyzer performs Bit, Word, Frame and Block
error measurements on the received data. The block
size can be programmed from 32 bits up to the
full pattern length (4MB). When using the analyzer’s
serial input, the data is broken into byte-wide
(i.e. 8 bit) word segments for word error measurements.
When using the analyzer’s parallel data
input, each bit can be treated as an independent
channel - each with its own error counter, to
make rapid error rate measurements without resorting
to channel sampling. This ensures accurate BER
measurement regardless of error distribution.
Histograms and graphs of ‘BER vs. Time’,
as well as other statistics, are calculated and
presented.
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